Evaluating Chip-Level Impact of Cu/Low-κ Performance Degradation on Circuit Performance at Future Technology Nodes

Dimensional scaling of interconnects at future technology generations presents major limitations to the improvement of the performances of integrated circuits. In this paper, we investigate the impact of highly scaled Cu/low-κ interconnects on the speed and power dissipation of multiple circuit blocks based on timing-closed full-chip Graphic Database System II (GDSII)-level layouts with detailed routing. First, we build multiple standard cell libraries for 45-, 22-, 11-, and 7-nm technology nodes and model their timing/power characteristics. Next, we pair these standard cell libraries with various interconnect files and build GDSII-level layouts for multiple benchmark circuits to study the sensitivity of the circuit performance and power dissipation to multiple interconnect technology parameters such as resistivity, barrier/liner thickness, and via resistance. We investigate the implications of slowing down interconnect dimensional scaling below 11-nm technology node.